;; Arm M-profile Vector Extension Machine Description
;; Copyright (C) 2019-2020 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful, but
;; WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
;; General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; .
(define_mode_iterator MVE_types [V16QI V8HI V4SI V2DI TI V8HF V4SF V2DF])
(define_mode_iterator MVE_VLD_ST [V16QI V8HI V4SI V8HF V4SF])
(define_mode_iterator MVE_0 [V8HF V4SF])
(define_mode_iterator MVE_1 [V16QI V8HI V4SI V2DI])
(define_mode_iterator MVE_3 [V16QI V8HI])
(define_mode_iterator MVE_2 [V16QI V8HI V4SI])
(define_mode_iterator MVE_5 [V8HI V4SI])
(define_mode_iterator MVE_6 [V8HI V4SI])
(define_c_enum "unspec" [VST4Q VRNDXQ_F VRNDQ_F VRNDPQ_F VRNDNQ_F VRNDMQ_F
VRNDAQ_F VREV64Q_F VNEGQ_F VDUPQ_N_F VABSQ_F VREV32Q_F
VCVTTQ_F32_F16 VCVTBQ_F32_F16 VCVTQ_TO_F_S VQNEGQ_S
VCVTQ_TO_F_U VREV16Q_S VREV16Q_U VADDLVQ_S VMVNQ_N_S
VMVNQ_N_U VCVTAQ_S VCVTAQ_U VREV64Q_S VREV64Q_U
VQABSQ_S VNEGQ_S VMVNQ_S VMVNQ_U VDUPQ_N_U VDUPQ_N_S
VCLZQ_U VCLZQ_S VCLSQ_S VADDVQ_S VADDVQ_U VABSQ_S
VREV32Q_U VREV32Q_S VMOVLTQ_U VMOVLTQ_S VMOVLBQ_S
VMOVLBQ_U VCVTQ_FROM_F_S VCVTQ_FROM_F_U VCVTPQ_S
VCVTPQ_U VCVTNQ_S VCVTNQ_U VCVTMQ_S VCVTMQ_U
VADDLVQ_U VCTP8Q VCTP16Q VCTP32Q VCTP64Q VPNOT
VCREATEQ_F VCVTQ_N_TO_F_S VCVTQ_N_TO_F_U VBRSRQ_N_F
VSUBQ_N_F VCREATEQ_U VCREATEQ_S VSHRQ_N_S VSHRQ_N_U
VCVTQ_N_FROM_F_S VCVTQ_N_FROM_F_U VADDLVQ_P_S
VADDLVQ_P_U VCMPNEQ_U VCMPNEQ_S VSHLQ_S VSHLQ_U VABDQ_S
VADDQ_N_S VADDVAQ_S VADDVQ_P_S VANDQ_S VBICQ_S
VBRSRQ_N_S VCADDQ_ROT270_S VCADDQ_ROT90_S VCMPEQQ_S
VCMPEQQ_N_S VCMPNEQ_N_S VEORQ_S VHADDQ_S VHADDQ_N_S
VHSUBQ_S VHSUBQ_N_S VMAXQ_S VMAXVQ_S VMINQ_S VMINVQ_S
VMLADAVQ_S VMULHQ_S VMULLBQ_INT_S VMULLTQ_INT_S VMULQ_S
VMULQ_N_S VORNQ_S VORRQ_S VQADDQ_S VQADDQ_N_S VQRSHLQ_S
VQRSHLQ_N_S VQSHLQ_S VQSHLQ_N_S VQSHLQ_R_S VQSUBQ_S
VQSUBQ_N_S VRHADDQ_S VRMULHQ_S VRSHLQ_S VRSHLQ_N_S
VRSHRQ_N_S VSHLQ_N_S VSHLQ_R_S VSUBQ_S VSUBQ_N_S
VABDQ_U VADDQ_N_U VADDVAQ_U VADDVQ_P_U VANDQ_U VBICQ_U
VBRSRQ_N_U VCADDQ_ROT270_U VCADDQ_ROT90_U VCMPEQQ_U
VCMPEQQ_N_U VCMPNEQ_N_U VEORQ_U VHADDQ_U VHADDQ_N_U
VHSUBQ_U VHSUBQ_N_U VMAXQ_U VMAXVQ_U VMINQ_U VMINVQ_U
VMLADAVQ_U VMULHQ_U VMULLBQ_INT_U VMULLTQ_INT_U VMULQ_U
VMULQ_N_U VORNQ_U VORRQ_U VQADDQ_U VQADDQ_N_U VQRSHLQ_U
VQRSHLQ_N_U VQSHLQ_U VQSHLQ_N_U VQSHLQ_R_U VQSUBQ_U
VQSUBQ_N_U VRHADDQ_U VRMULHQ_U VRSHLQ_U VRSHLQ_N_U
VRSHRQ_N_U VSHLQ_N_U VSHLQ_R_U VSUBQ_U VSUBQ_N_U
VCMPGEQ_N_S VCMPGEQ_S VCMPGTQ_N_S VCMPGTQ_S VCMPLEQ_N_S
VCMPLEQ_S VCMPLTQ_N_S VCMPLTQ_S VHCADDQ_ROT270_S
VHCADDQ_ROT90_S VMAXAQ_S VMAXAVQ_S VMINAQ_S VMINAVQ_S
VMLADAVXQ_S VMLSDAVQ_S VMLSDAVXQ_S VQDMULHQ_N_S
VQDMULHQ_S VQRDMULHQ_N_S VQRDMULHQ_S VQSHLUQ_N_S
VCMPCSQ_N_U VCMPCSQ_U VCMPHIQ_N_U VCMPHIQ_U VABDQ_M_S
VABDQ_M_U VABDQ_F VADDQ_N_F VANDQ_F VBICQ_F
VCADDQ_ROT270_F VCADDQ_ROT90_F VCMPEQQ_F VCMPEQQ_N_F
VCMPGEQ_F VCMPGEQ_N_F VCMPGTQ_F VCMPGTQ_N_F VCMPLEQ_F
VCMPLEQ_N_F VCMPLTQ_F VCMPLTQ_N_F VCMPNEQ_F VCMPNEQ_N_F
VCMULQ_F VCMULQ_ROT180_F VCMULQ_ROT270_F VCMULQ_ROT90_F
VEORQ_F VMAXNMAQ_F VMAXNMAVQ_F VMAXNMQ_F VMAXNMVQ_F
VMINNMAQ_F VMINNMAVQ_F VMINNMQ_F VMINNMVQ_F VMULQ_F
VMULQ_N_F VORNQ_F VORRQ_F VSUBQ_F VADDLVAQ_U
VADDLVAQ_S VBICQ_N_U VBICQ_N_S VCTP8Q_M VCTP16Q_M
VCTP32Q_M VCTP64Q_M VCVTBQ_F16_F32 VCVTTQ_F16_F32
VMLALDAVQ_U VMLALDAVXQ_U VMLALDAVXQ_S VMLALDAVQ_S
VMLSLDAVQ_S VMLSLDAVXQ_S VMOVNBQ_U VMOVNBQ_S
VMOVNTQ_U VMOVNTQ_S VORRQ_N_S VORRQ_N_U VQDMULLBQ_N_S
VQDMULLBQ_S VQDMULLTQ_N_S VQDMULLTQ_S VQMOVNBQ_U
VQMOVNBQ_S VQMOVUNBQ_S VQMOVUNTQ_S VRMLALDAVHXQ_S
VRMLSLDAVHQ_S VRMLSLDAVHXQ_S VSHLLBQ_S
VSHLLBQ_U VSHLLTQ_U VSHLLTQ_S VQMOVNTQ_U VQMOVNTQ_S
VSHLLBQ_N_S VSHLLBQ_N_U VSHLLTQ_N_U VSHLLTQ_N_S
VRMLALDAVHQ_U VRMLALDAVHQ_S VMULLTQ_POLY_P
VMULLBQ_POLY_P VBICQ_M_N_S VBICQ_M_N_U VCMPEQQ_M_F
VCVTAQ_M_S VCVTAQ_M_U VCVTQ_M_TO_F_S VCVTQ_M_TO_F_U
VQRSHRNBQ_N_U VQRSHRNBQ_N_S VQRSHRUNBQ_N_S
VRMLALDAVHAQ_S VABAVQ_S VABAVQ_U VSHLCQ_S VSHLCQ_U
VRMLALDAVHAQ_U VABSQ_M_S VADDVAQ_P_S VADDVAQ_P_U
VCLSQ_M_S VCLZQ_M_S VCLZQ_M_U VCMPCSQ_M_N_U
VCMPCSQ_M_U VCMPEQQ_M_N_S VCMPEQQ_M_N_U VCMPEQQ_M_S
VCMPEQQ_M_U VCMPGEQ_M_N_S VCMPGEQ_M_S VCMPGTQ_M_N_S
VCMPGTQ_M_S VCMPHIQ_M_N_U VCMPHIQ_M_U VCMPLEQ_M_N_S
VCMPLEQ_M_S VCMPLTQ_M_N_S VCMPLTQ_M_S VCMPNEQ_M_N_S
VCMPNEQ_M_N_U VCMPNEQ_M_S VCMPNEQ_M_U VDUPQ_M_N_S
VDUPQ_M_N_U VDWDUPQ_N_U VDWDUPQ_WB_U VIWDUPQ_N_U
VIWDUPQ_WB_U VMAXAQ_M_S VMAXAVQ_P_S VMAXVQ_P_S
VMAXVQ_P_U VMINAQ_M_S VMINAVQ_P_S VMINVQ_P_S VMINVQ_P_U
VMLADAVAQ_S VMLADAVAQ_U VMLADAVQ_P_S VMLADAVQ_P_U
VMLADAVXQ_P_S VMLAQ_N_S VMLAQ_N_U VMLASQ_N_S VMLASQ_N_U
VMLSDAVQ_P_S VMLSDAVXQ_P_S VMVNQ_M_S VMVNQ_M_U
VNEGQ_M_S VPSELQ_S VPSELQ_U VQABSQ_M_S VQDMLAHQ_N_S
VQDMLAHQ_N_U VQNEGQ_M_S VQRDMLADHQ_S VQRDMLADHXQ_S
VQRDMLAHQ_N_S VQRDMLAHQ_N_U VQRDMLASHQ_N_S
VQRDMLASHQ_N_U VQRDMLSDHQ_S VQRDMLSDHXQ_S VQRSHLQ_M_N_S
VQRSHLQ_M_N_U VQSHLQ_M_R_S VQSHLQ_M_R_U VREV64Q_M_S
VREV64Q_M_U VRSHLQ_M_N_S VRSHLQ_M_N_U VSHLQ_M_R_S
VSHLQ_M_R_U VSLIQ_N_S VSLIQ_N_U VSRIQ_N_S VSRIQ_N_U
VQDMLSDHXQ_S VQDMLSDHQ_S VQDMLADHXQ_S VQDMLADHQ_S
VMLSDAVAXQ_S VMLSDAVAQ_S VMLADAVAXQ_S
VCMPGEQ_M_F VCMPGTQ_M_N_F VMLSLDAVQ_P_S VRMLALDAVHAXQ_S
VMLSLDAVXQ_P_S VFMAQ_F VMLSLDAVAQ_S VQSHRUNBQ_N_S
VQRSHRUNTQ_N_S VCMLAQ_F VMINNMAQ_M_F VFMASQ_N_F
VDUPQ_M_N_F VCMPGTQ_M_F VCMPLTQ_M_F VRMLSLDAVHQ_P_S
VQSHRUNTQ_N_S VABSQ_M_F VMAXNMAVQ_P_F VFMAQ_N_F
VRMLSLDAVHXQ_P_S VREV32Q_M_F VRMLSLDAVHAQ_S
VRMLSLDAVHAXQ_S VCMPLTQ_M_N_F VCMPNEQ_M_F VRNDAQ_M_F
VRNDPQ_M_F VADDLVAQ_P_S VQMOVUNBQ_M_S VCMPLEQ_M_F
VCMLAQ_ROT180_F VMLSLDAVAXQ_S VRNDXQ_M_F VFMSQ_F
VMINNMVQ_P_F VMAXNMVQ_P_F VPSELQ_F VCMLAQ_ROT90_F
VQMOVUNTQ_M_S VREV64Q_M_F VNEGQ_M_F VRNDMQ_M_F
VCMPLEQ_M_N_F VCMPGEQ_M_N_F VRNDNQ_M_F VMINNMAVQ_P_F
VCMPNEQ_M_N_F VRMLALDAVHQ_P_S VRMLALDAVHXQ_P_S
VCMPEQQ_M_N_F VCMLAQ_ROT270_F VMAXNMAQ_M_F VRNDQ_M_F
VMLALDAVQ_P_U VMLALDAVQ_P_S VQMOVNBQ_M_S VQMOVNBQ_M_U
VMOVLTQ_M_U VMOVLTQ_M_S VMOVNBQ_M_U VMOVNBQ_M_S
VRSHRNTQ_N_U VRSHRNTQ_N_S VORRQ_M_N_S VORRQ_M_N_U
VREV32Q_M_S VREV32Q_M_U VQRSHRNTQ_N_U VQRSHRNTQ_N_S
VMOVNTQ_M_U VMOVNTQ_M_S VMOVLBQ_M_U VMOVLBQ_M_S
VMLALDAVAQ_S VMLALDAVAQ_U VQSHRNBQ_N_U VQSHRNBQ_N_S
VSHRNBQ_N_U VSHRNBQ_N_S VRSHRNBQ_N_S VRSHRNBQ_N_U
VMLALDAVXQ_P_U VMLALDAVXQ_P_S VQMOVNTQ_M_U VQMOVNTQ_M_S
VMVNQ_M_N_U VMVNQ_M_N_S VQSHRNTQ_N_U VQSHRNTQ_N_S
VMLALDAVAXQ_S VMLALDAVAXQ_U VSHRNTQ_N_S VSHRNTQ_N_U
VCVTBQ_M_F16_F32 VCVTBQ_M_F32_F16 VCVTTQ_M_F16_F32
VCVTTQ_M_F32_F16 VCVTMQ_M_S VCVTMQ_M_U VCVTNQ_M_S
VCVTPQ_M_S VCVTPQ_M_U VCVTQ_M_N_FROM_F_S VCVTNQ_M_U
VREV16Q_M_S VREV16Q_M_U VREV32Q_M VCVTQ_M_FROM_F_U
VCVTQ_M_FROM_F_S VRMLALDAVHQ_P_U VADDLVAQ_P_U
VCVTQ_M_N_FROM_F_U VQSHLUQ_M_N_S VABAVQ_P_S
VABAVQ_P_U VSHLQ_M_S VSHLQ_M_U VSRIQ_M_N_S
VSRIQ_M_N_U VSUBQ_M_U VSUBQ_M_S VCVTQ_M_N_TO_F_U
VCVTQ_M_N_TO_F_S VQADDQ_M_U VQADDQ_M_S
VRSHRQ_M_N_S VSUBQ_M_N_S VSUBQ_M_N_U VBRSRQ_M_N_S
VSUBQ_M_N_F VBICQ_M_F VHADDQ_M_U VBICQ_M_U VBICQ_M_S
VMULQ_M_N_U VHADDQ_M_S VORNQ_M_F VMLAQ_M_N_S VQSUBQ_M_U
VQSUBQ_M_S VMLAQ_M_N_U VQSUBQ_M_N_U VQSUBQ_M_N_S
VMULLTQ_INT_M_S VMULLTQ_INT_M_U VMULQ_M_N_S VMULQ_M_N_F
VMLASQ_M_N_U VMLASQ_M_N_S VMAXQ_M_U VQRDMLAHQ_M_N_U
VCADDQ_ROT270_M_F VCADDQ_ROT270_M_U VCADDQ_ROT270_M_S
VQRSHLQ_M_S VMULQ_M_F VRHADDQ_M_U VSHRQ_M_N_U
VRHADDQ_M_S VMULQ_M_S VMULQ_M_U VQRDMLASHQ_M_N_S
VRSHLQ_M_S VRSHLQ_M_U VRSHRQ_M_N_U VADDQ_M_N_F
VADDQ_M_N_S VADDQ_M_N_U VQRDMLASHQ_M_N_U VMAXQ_M_S
VQRDMLAHQ_M_N_S VORRQ_M_S VORRQ_M_U VORRQ_M_F
VQRSHLQ_M_U VRMULHQ_M_U VRMULHQ_M_S VMINQ_M_S VMINQ_M_U
VANDQ_M_F VANDQ_M_U VANDQ_M_S VHSUBQ_M_N_S VHSUBQ_M_N_U
VMULHQ_M_S VMULHQ_M_U VMULLBQ_INT_M_U
VMULLBQ_INT_M_S VCADDQ_ROT90_M_F
VSHRQ_M_N_S VADDQ_M_U VSLIQ_M_N_U
VQADDQ_M_N_S VBRSRQ_M_N_F VABDQ_M_F VBRSRQ_M_N_U
VEORQ_M_F VSHLQ_M_N_S VQDMLAHQ_M_N_U VQDMLAHQ_M_N_S
VSHLQ_M_N_U VMLADAVAQ_P_U VMLADAVAQ_P_S VSLIQ_M_N_S
VQSHLQ_M_U VQSHLQ_M_S VCADDQ_ROT90_M_U VCADDQ_ROT90_M_S
VORNQ_M_U VORNQ_M_S VQSHLQ_M_N_S VQSHLQ_M_N_U VADDQ_M_S
VHADDQ_M_N_S VADDQ_M_F VQADDQ_M_N_U VEORQ_M_S VEORQ_M_U
VHSUBQ_M_S VHSUBQ_M_U VHADDQ_M_N_U VHCADDQ_ROT90_M_S
VQRDMLSDHQ_M_S VQRDMLSDHXQ_M_S VQRDMLADHXQ_M_S
VQDMULHQ_M_S VMLADAVAXQ_P_S VQDMLADHXQ_M_S
VQRDMULHQ_M_S VMLSDAVAXQ_P_S VQDMULHQ_M_N_S
VHCADDQ_ROT270_M_S VQDMLSDHQ_M_S VQDMLSDHXQ_M_S
VMLSDAVAQ_P_S VQRDMLADHQ_M_S VQDMLADHQ_M_S
VMLALDAVAQ_P_U VMLALDAVAQ_P_S VMLALDAVAXQ_P_U
VQRSHRNBQ_M_N_U VQRSHRNBQ_M_N_S VQRSHRNTQ_M_N_S
VQSHRNBQ_M_N_U VQSHRNBQ_M_N_S VQSHRNTQ_M_N_S
VRSHRNBQ_M_N_U VRSHRNBQ_M_N_S VRSHRNTQ_M_N_U
VSHLLBQ_M_N_U VSHLLBQ_M_N_S VSHLLTQ_M_N_U VSHLLTQ_M_N_S
VSHRNBQ_M_N_S VSHRNBQ_M_N_U VSHRNTQ_M_N_S VSHRNTQ_M_N_U
VMLALDAVAXQ_P_S VQRSHRNTQ_M_N_U VQSHRNTQ_M_N_U
VRSHRNTQ_M_N_S VQRDMULHQ_M_N_S VRMLALDAVHAQ_P_S
VMLSLDAVAQ_P_S VMLSLDAVAXQ_P_S VMULLBQ_POLY_M_P
VMULLTQ_POLY_M_P VQDMULLBQ_M_N_S VQDMULLBQ_M_S
VQDMULLTQ_M_N_S VQDMULLTQ_M_S VQRSHRUNBQ_M_N_S
VQRSHRUNTQ_M_N_SVQSHRUNBQ_M_N_S VQSHRUNTQ_M_N_S
VRMLALDAVHAQ_P_U VRMLALDAVHAXQ_P_S VRMLSLDAVHAQ_P_S
VRMLSLDAVHAXQ_P_S VQRSHRUNTQ_M_N_S VQSHRUNBQ_M_N_S
VCMLAQ_M_F VCMLAQ_ROT180_M_F VCMLAQ_ROT270_M_F
VCMLAQ_ROT90_M_F VCMULQ_M_F VCMULQ_ROT180_M_F
VCMULQ_ROT270_M_F VCMULQ_ROT90_M_F VFMAQ_M_F
VFMAQ_M_N_F VFMASQ_M_N_F VFMSQ_M_F VMAXNMQ_M_F
VMINNMQ_M_F VSUBQ_M_F VSTRWQSB_S VSTRWQSB_U
VSTRBQSO_S VSTRBQSO_U VSTRBQ_S VSTRBQ_U VLDRBQGO_S
VLDRBQGO_U VLDRBQ_S VLDRBQ_U VLDRWQGB_S VLDRWQGB_U
VLD1Q_F VLD1Q_S VLD1Q_U VLDRHQ_F VLDRHQGO_S
VLDRHQGO_U VLDRHQGSO_S VLDRHQGSO_U VLDRHQ_S VLDRHQ_U
VLDRWQ_F VLDRWQ_S VLDRWQ_U VLDRDQGB_S VLDRDQGB_U
VLDRDQGO_S VLDRDQGO_U VLDRDQGSO_S VLDRDQGSO_U
VLDRHQGO_F VLDRHQGSO_F VLDRWQGB_F VLDRWQGO_F
VLDRWQGO_S VLDRWQGO_U VLDRWQGSO_F VLDRWQGSO_S
VLDRWQGSO_U VSTRHQ_F VST1Q_S VST1Q_U VSTRHQSO_S
VSTRHQSO_U VSTRHQSSO_S VSTRHQSSO_U VSTRHQ_S
VSTRHQ_U VSTRWQ_S VSTRWQ_U VSTRWQ_F VST1Q_F VSTRDQSB_S
VSTRDQSB_U VSTRDQSO_S VSTRDQSO_U VSTRDQSSO_S
VSTRDQSSO_U VSTRWQSO_S VSTRWQSO_U VSTRWQSSO_S
VSTRWQSSO_U VSTRHQSO_F VSTRHQSSO_F VSTRWQSB_F
VSTRWQSO_F VSTRWQSSO_F VDDUPQ VDDUPQ_M VDWDUPQ
VDWDUPQ_M VIDUPQ VIDUPQ_M VIWDUPQ VIWDUPQ_M
VSTRWQSBWB_S VSTRWQSBWB_U VLDRWQGBWB_S VLDRWQGBWB_U
VSTRWQSBWB_F VLDRWQGBWB_F VSTRDQSBWB_S VSTRDQSBWB_U
VLDRDQGBWB_S VLDRDQGBWB_U VADCQ_U VADCQ_M_U VADCQ_S
VADCQ_M_S VSBCIQ_U VSBCIQ_S VSBCIQ_M_U VSBCIQ_M_S
VSBCQ_U VSBCQ_S VSBCQ_M_U VSBCQ_M_S VADCIQ_U VADCIQ_M_U
VADCIQ_S VADCIQ_M_S VLD2Q VLD4Q VST2Q SRSHRL SRSHR
URSHR URSHRL SQRSHR UQRSHL UQRSHLL_64 VSHLCQ_M_U
UQRSHLL_48 SQRSHRL_64 SQRSHRL_48 VSHLCQ_M_S])
(define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI")
(V4SF "V4SI")])
(define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u") (VREV16Q_S "s")
(VREV16Q_U "u") (VMVNQ_N_S "s") (VMVNQ_N_U "u")
(VCVTAQ_U "u") (VCVTAQ_S "s") (VREV64Q_S "s")
(VREV64Q_U "u") (VMVNQ_S "s") (VMVNQ_U "u")
(VDUPQ_N_U "u") (VDUPQ_N_S"s") (VADDVQ_S "s")
(VADDVQ_U "u") (VADDVQ_S "s") (VADDVQ_U "u")
(VMOVLTQ_U "u") (VMOVLTQ_S "s") (VMOVLBQ_S "s")
(VMOVLBQ_U "u") (VCVTQ_FROM_F_S "s") (VCVTQ_FROM_F_U "u")
(VCVTPQ_S "s") (VCVTPQ_U "u") (VCVTNQ_S "s")
(VCVTNQ_U "u") (VCVTMQ_S "s") (VCVTMQ_U "u")
(VCLZQ_U "u") (VCLZQ_S "s") (VREV32Q_U "u")
(VREV32Q_S "s") (VADDLVQ_U "u") (VADDLVQ_S "s")
(VCVTQ_N_TO_F_S "s") (VCVTQ_N_TO_F_U "u")
(VCREATEQ_U "u") (VCREATEQ_S "s") (VSHRQ_N_S "s")
(VSHRQ_N_U "u") (VCVTQ_N_FROM_F_S "s") (VSHLQ_U "u")
(VCVTQ_N_FROM_F_U "u") (VADDLVQ_P_S "s") (VSHLQ_S "s")
(VADDLVQ_P_U "u") (VCMPNEQ_U "u") (VCMPNEQ_S "s")
(VABDQ_M_S "s") (VABDQ_M_U "u") (VABDQ_S "s")
(VABDQ_U "u") (VADDQ_N_S "s") (VADDQ_N_U "u")
(VADDVQ_P_S "s") (VADDVQ_P_U "u") (VANDQ_S "s")
(VANDQ_U "u") (VBICQ_S "s") (VBICQ_U "u")
(VBRSRQ_N_S "s") (VBRSRQ_N_U "u") (VCADDQ_ROT270_S "s")
(VCADDQ_ROT270_U "u") (VCADDQ_ROT90_S "s")
(VCMPEQQ_S "s") (VCMPEQQ_U "u") (VCADDQ_ROT90_U "u")
(VCMPEQQ_N_S "s") (VCMPEQQ_N_U "u") (VCMPNEQ_N_S "s")
(VCMPNEQ_N_U "u") (VEORQ_S "s") (VEORQ_U "u")
(VHADDQ_N_S "s") (VHADDQ_N_U "u") (VHADDQ_S "s")
(VHADDQ_U "u") (VHSUBQ_N_S "s") (VHSUBQ_N_U "u")
(VHSUBQ_S "s") (VMAXQ_S "s") (VMAXQ_U "u") (VHSUBQ_U "u")
(VMAXVQ_S "s") (VMAXVQ_U "u") (VMINQ_S "s") (VMINQ_U "u")
(VMINVQ_S "s") (VMINVQ_U "u") (VMLADAVQ_S "s")
(VMLADAVQ_U "u") (VMULHQ_S "s") (VMULHQ_U "u")
(VMULLBQ_INT_S "s") (VMULLBQ_INT_U "u") (VQADDQ_S "s")
(VMULLTQ_INT_S "s") (VMULLTQ_INT_U "u") (VQADDQ_U "u")
(VMULQ_N_S "s") (VMULQ_N_U "u") (VMULQ_S "s")
(VMULQ_U "u") (VORNQ_S "s") (VORNQ_U "u") (VORRQ_S "s")
(VORRQ_U "u") (VQADDQ_N_S "s") (VQADDQ_N_U "u")
(VQRSHLQ_N_S "s") (VQRSHLQ_N_U "u") (VQRSHLQ_S "s")
(VQRSHLQ_U "u") (VQSHLQ_N_S "s") (VQSHLQ_N_U "u")
(VQSHLQ_R_S "s") (VQSHLQ_R_U "u") (VQSHLQ_S "s")
(VQSHLQ_U "u") (VQSUBQ_N_S "s") (VQSUBQ_N_U "u")
(VQSUBQ_S "s") (VQSUBQ_U "u") (VRHADDQ_S "s")
(VRHADDQ_U "u") (VRMULHQ_S "s") (VRMULHQ_U "u")
(VRSHLQ_N_S "s") (VRSHLQ_N_U "u") (VRSHLQ_S "s")
(VRSHLQ_U "u") (VRSHRQ_N_S "s") (VRSHRQ_N_U "u")
(VSHLQ_N_S "s") (VSHLQ_N_U "u") (VSHLQ_R_S "s")
(VSHLQ_R_U "u") (VSUBQ_N_S "s") (VSUBQ_N_U "u")
(VSUBQ_S "s") (VSUBQ_U "u") (VADDVAQ_S "s")
(VADDVAQ_U "u") (VADDLVAQ_S "s") (VADDLVAQ_U "u")
(VBICQ_N_S "s") (VBICQ_N_U "u") (VMLALDAVQ_U "u")
(VMLALDAVQ_S "s") (VMLALDAVXQ_U "u") (VMLALDAVXQ_S "s")
(VMOVNBQ_U "u") (VMOVNBQ_S "s") (VMOVNTQ_U "u")
(VMOVNTQ_S "s") (VORRQ_N_S "s") (VORRQ_N_U "u")
(VQMOVNBQ_U "u") (VQMOVNBQ_S "s") (VQMOVNTQ_S "s")
(VQMOVNTQ_U "u") (VSHLLBQ_N_U "u") (VSHLLBQ_N_S "s")
(VSHLLTQ_N_U "u") (VSHLLTQ_N_S "s") (VRMLALDAVHQ_U "u")
(VRMLALDAVHQ_S "s") (VBICQ_M_N_S "s") (VBICQ_M_N_U "u")
(VCVTAQ_M_S "s") (VCVTAQ_M_U "u") (VCVTQ_M_TO_F_S "s")
(VCVTQ_M_TO_F_U "u") (VQRSHRNBQ_N_S "s")
(VQRSHRNBQ_N_U "u") (VABAVQ_S "s") (VABAVQ_U "u")
(VRMLALDAVHAQ_U "u") (VRMLALDAVHAQ_S "s") (VSHLCQ_S "s")
(VSHLCQ_U "u") (VADDVAQ_P_S "s") (VADDVAQ_P_U "u")
(VCLZQ_M_S "s") (VCLZQ_M_U "u") (VCMPEQQ_M_N_S "s")
(VCMPEQQ_M_N_U "u") (VCMPEQQ_M_S "s") (VCMPEQQ_M_U "u")
(VCMPNEQ_M_N_S "s") (VCMPNEQ_M_N_U "u") (VCMPNEQ_M_S "s")
(VCMPNEQ_M_U "u") (VDUPQ_M_N_S "s") (VDUPQ_M_N_U "u")
(VMAXVQ_P_S "s") (VMAXVQ_P_U "u") (VMINVQ_P_S "s")
(VMINVQ_P_U "u") (VMLADAVAQ_S "s") (VMLADAVAQ_U "u")
(VMLADAVQ_P_S "s") (VMLADAVQ_P_U "u") (VMLAQ_N_S "s")
(VMLAQ_N_U "u") (VMLASQ_N_S "s") (VMLASQ_N_U "u")
(VMVNQ_M_S "s") (VMVNQ_M_U "u") (VPSELQ_S "s")
(VPSELQ_U "u") (VQDMLAHQ_N_S "s") (VQDMLAHQ_N_U "u")
(VQRDMLAHQ_N_S "s") (VQRDMLAHQ_N_U "u")
(VQRDMLASHQ_N_S "s") (VQRDMLASHQ_N_U "u")
(VQRSHLQ_M_N_S "s") (VQRSHLQ_M_N_U "u")
(VQSHLQ_M_R_S "s") (VQSHLQ_M_R_U "u") (VSRIQ_N_S "s")
(VREV64Q_M_S "s") (VREV64Q_M_U "u") (VSRIQ_N_U "u")
(VRSHLQ_M_N_S "s") (VRSHLQ_M_N_U "u") (VSHLQ_M_R_S "s")
(VSHLQ_M_R_U "u") (VSLIQ_N_S "s") (VSLIQ_N_U "u")
(VMLALDAVQ_P_S "s") (VQMOVNBQ_M_S "s") (VMOVLTQ_M_S "s")
(VMOVNBQ_M_S "s") (VRSHRNTQ_N_S "s") (VORRQ_M_N_S "s")
(VREV32Q_M_S "s") (VQRSHRNTQ_N_S "s") (VMOVNTQ_M_S "s")
(VMOVLBQ_M_S "s") (VMLALDAVAQ_S "s") (VQSHRNBQ_N_S "s")
(VSHRNBQ_N_S "s") (VRSHRNBQ_N_S "s") (VMLALDAVXQ_P_S "s")
(VQMOVNTQ_M_S "s") (VMVNQ_M_N_S "s") (VQSHRNTQ_N_S "s")
(VMLALDAVAXQ_S "s") (VSHRNTQ_N_S "s") (VMLALDAVQ_P_U "u")
(VQMOVNBQ_M_U "u") (VMOVLTQ_M_U "u") (VMOVNBQ_M_U "u")
(VRSHRNTQ_N_U "u") (VORRQ_M_N_U "u") (VREV32Q_M_U "u")
(VREV16Q_M_S "s") (VREV16Q_M_U "u")
(VQRSHRNTQ_N_U "u") (VMOVNTQ_M_U "u") (VMOVLBQ_M_U "u")
(VMLALDAVAQ_U "u") (VQSHRNBQ_N_U "u") (VSHRNBQ_N_U "u")
(VRSHRNBQ_N_U "u") (VMLALDAVXQ_P_U "u")
(VMVNQ_M_N_U "u") (VQSHRNTQ_N_U "u") (VMLALDAVAXQ_U "u")
(VQMOVNTQ_M_U "u") (VSHRNTQ_N_U "u") (VCVTMQ_M_S "s")
(VCVTMQ_M_U "u") (VCVTNQ_M_S "s") (VCVTNQ_M_U "u")
(VCVTPQ_M_S "s") (VCVTPQ_M_U "u") (VADDLVAQ_P_S "s")
(VCVTQ_M_N_FROM_F_U "u") (VCVTQ_M_FROM_F_S "s")
(VCVTQ_M_FROM_F_U "u") (VRMLALDAVHQ_P_U "u")
(VRMLALDAVHQ_P_S "s") (VADDLVAQ_P_U "u")
(VCVTQ_M_N_FROM_F_S "s") (VABAVQ_P_U "u")
(VABAVQ_P_S "s") (VSHLQ_M_S "s") (VSHLQ_M_U "u")
(VSRIQ_M_N_S "s") (VSRIQ_M_N_U "u") (VSUBQ_M_S "s")
(VSUBQ_M_U "u") (VCVTQ_M_N_TO_F_S "s")
(VCVTQ_M_N_TO_F_U "u") (VADDQ_M_N_U "u")
(VSHLQ_M_N_S "s") (VMAXQ_M_U "u") (VHSUBQ_M_N_U "u")
(VMULQ_M_N_S "s") (VQSHLQ_M_U "u") (VRHADDQ_M_S "s")
(VEORQ_M_U "u") (VSHRQ_M_N_U "u") (VCADDQ_ROT90_M_U "u")
(VMLADAVAQ_P_U "u") (VEORQ_M_S "s") (VBRSRQ_M_N_S "s")
(VMULQ_M_U "u") (VQRDMLAHQ_M_N_S "s") (VHSUBQ_M_N_S "s")
(VQRSHLQ_M_S "s") (VMULQ_M_N_U "u")
(VMULQ_M_S "s") (VQSHLQ_M_N_U "u") (VSLIQ_M_N_U "u")
(VMLADAVAQ_P_S "s") (VQRSHLQ_M_U "u")
(VMULLBQ_INT_M_U "u") (VSHLQ_M_N_U "u") (VQSUBQ_M_U "u")
(VQRDMLASHQ_M_N_U "u") (VRSHRQ_M_N_S "s")
(VORNQ_M_S "s") (VCADDQ_ROT270_M_S "s") (VRHADDQ_M_U "u")
(VRSHRQ_M_N_U "u") (VMLASQ_M_N_U "u") (VHSUBQ_M_U "u")
(VQSUBQ_M_N_S "s") (VMULLTQ_INT_M_S "s")
(VORRQ_M_S "s") (VQDMLAHQ_M_N_U "u") (VRSHLQ_M_S "s")
(VHADDQ_M_U "u") (VHADDQ_M_N_S "s") (VMULLTQ_INT_M_U "u")
(VORRQ_M_U "u") (VHADDQ_M_S "s") (VHADDQ_M_N_U "u")
(VQDMLAHQ_M_N_S "s") (VMAXQ_M_S "s") (VORNQ_M_U "u")
(VCADDQ_ROT270_M_U "u") (VQADDQ_M_U "u")
(VQRDMLASHQ_M_N_S "s") (VBICQ_M_U "u") (VMINQ_M_U "u")
(VSUBQ_M_N_S "s") (VMULLBQ_INT_M_S "s") (VQSUBQ_M_S "s")
(VCADDQ_ROT90_M_S "s") (VRMULHQ_M_S "s") (VANDQ_M_U "u")
(VMULHQ_M_S "s") (VADDQ_M_S "s") (VQRDMLAHQ_M_N_U "u")
(VMLASQ_M_N_S "s") (VHSUBQ_M_S "s") (VRMULHQ_M_U "u")
(VQADDQ_M_N_S "s") (VSHRQ_M_N_S "s") (VANDQ_M_S "s")
(VABDQ_M_U "u") (VQSHLQ_M_S "s") (VABDQ_M_S "s")
(VSUBQ_M_N_U "u") (VMLAQ_M_N_S "s") (VBRSRQ_M_N_U "u")
(VADDQ_M_U "u") (VRSHLQ_M_U "u") (VSLIQ_M_N_S "s")
(VQADDQ_M_N_U "u") (VADDQ_M_N_S "s") (VQSUBQ_M_N_U "u")
(VMLAQ_M_N_U "u") (VMINQ_M_S "s") (VMULHQ_M_U "u")
(VQADDQ_M_S "s") (VBICQ_M_S "s") (VQSHLQ_M_N_S "s")
(VQSHRNTQ_M_N_S "s") (VQSHRNTQ_M_N_U "u")
(VSHRNTQ_M_N_U "u") (VSHRNTQ_M_N_S "s")
(VSHRNBQ_M_N_S "s") (VSHRNBQ_M_N_U "u")
(VSHLLTQ_M_N_S "s") (VSHLLTQ_M_N_U "u")
(VSHLLBQ_M_N_S "s") (VSHLLBQ_M_N_U "u")
(VRSHRNTQ_M_N_S "s") (VRSHRNTQ_M_N_U "u")
(VRSHRNBQ_M_N_U "u") (VRSHRNBQ_M_N_S "s")
(VQSHRNTQ_M_N_U "u") (VQSHRNTQ_M_N_S "s")
(VQSHRNBQ_M_N_S "s") (VQSHRNBQ_M_N_U "u")
(VQRSHRNTQ_M_N_S "s") (VQRSHRNTQ_M_N_U "u")
(VQRSHRNBQ_M_N_S "s") (VQRSHRNBQ_M_N_U "u")
(VMLALDAVAXQ_P_S "s") (VMLALDAVAXQ_P_U "u")
(VMLALDAVAQ_P_S "s") (VMLALDAVAQ_P_U "u")
(VSTRWQSB_S "s") (VSTRWQSB_U "u") (VSTRBQSO_S "s")
(VSTRBQSO_U "u") (VSTRBQ_S "s") (VSTRBQ_U "u")
(VLDRBQGO_S "s") (VLDRBQGO_U "u") (VLDRBQ_S "s")
(VLDRBQ_U "u") (VLDRWQGB_S "s") (VLDRWQGB_U "u")
(VLD1Q_S "s") (VLD1Q_U "u") (VLDRHQGO_S "s")
(VLDRHQGO_U "u") (VLDRHQGSO_S "s") (VLDRHQGSO_U "u")
(VLDRHQ_S "s") (VLDRHQ_U "u") (VLDRWQ_S "s")
(VLDRWQ_U "u") (VLDRDQGB_S "s") (VLDRDQGB_U "u")
(VLDRDQGO_S "s") (VLDRDQGO_U "u") (VLDRDQGSO_S "s")
(VLDRDQGSO_U "u") (VLDRWQGO_S "s") (VLDRWQGO_U "u")
(VLDRWQGSO_S "s") (VLDRWQGSO_U "u") (VST1Q_S "s")
(VST1Q_U "u") (VSTRHQSO_S "s") (VSTRHQSO_U "u")
(VSTRHQSSO_S "s") (VSTRHQSSO_U "u") (VSTRHQ_S "s")
(VSTRHQ_U "u") (VSTRWQ_S "s") (VSTRWQ_U "u")
(VSTRDQSB_S "s") (VSTRDQSB_U "u") (VSTRDQSO_S "s")
(VSTRDQSO_U "u") (VSTRDQSSO_S "s") (VSTRDQSSO_U "u")
(VSTRWQSO_U "u") (VSTRWQSO_S "s") (VSTRWQSSO_U "u")
(VSTRWQSSO_S "s") (VSTRWQSBWB_S "s") (VSTRWQSBWB_U "u")
(VLDRWQGBWB_S "s") (VLDRWQGBWB_U "u") (VLDRDQGBWB_S "s")
(VLDRDQGBWB_U "u") (VSTRDQSBWB_S "s") (VADCQ_M_S "s")
(VSTRDQSBWB_U "u") (VSBCQ_U "u") (VSBCQ_M_U "u")
(VSBCQ_S "s") (VSBCQ_M_S "s") (VSBCIQ_U "u")
(VSBCIQ_M_U "u") (VSBCIQ_S "s") (VSBCIQ_M_S "s")
(VADCQ_U "u") (VADCQ_M_U "u") (VADCQ_S "s")
(VADCIQ_U "u") (VADCIQ_M_U "u") (VADCIQ_S "s")
(VADCIQ_M_S "s") (SQRSHRL_64 "64") (SQRSHRL_48 "48")
(UQRSHLL_64 "64") (UQRSHLL_48 "48") (VSHLCQ_M_S "s")
(VSHLCQ_M_U "u")])
(define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32")
(VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16")
(VCTP32Q_M "32") (VCTP64Q_M "64")])
(define_mode_attr MVE_pred2 [(V16QI "mve_imm_8") (V8HI "mve_imm_16")
(V4SI "mve_imm_32")
(V8HF "mve_imm_16") (V4SF "mve_imm_32")])
(define_mode_attr MVE_constraint2 [(V16QI "Rb") (V8HI "Rd") (V4SI "Rf")
(V8HF "Rd") (V4SF "Rf")])
(define_mode_attr MVE_LANES [(V16QI "16") (V8HI "8") (V4SI "4")])
(define_mode_attr MVE_constraint [ (V16QI "Ra") (V8HI "Rc") (V4SI "Re")])
(define_mode_attr MVE_pred [ (V16QI "mve_imm_7") (V8HI "mve_imm_15")
(V4SI "mve_imm_31")])
(define_mode_attr MVE_constraint3 [ (V8HI "Rb") (V4SI "Rd")])
(define_mode_attr MVE_pred3 [ (V8HI "mve_imm_8") (V4SI "mve_imm_16")])
(define_mode_attr MVE_constraint1 [ (V8HI "Ra") (V4SI "Rc")])
(define_mode_attr MVE_pred1 [ (V8HI "mve_imm_7") (V4SI "mve_imm_15")])
(define_mode_attr MVE_B_ELEM [ (V16QI "V16QI") (V8HI "V8QI") (V4SI "V4QI")])
(define_mode_attr MVE_H_ELEM [ (V8HI "V8HI") (V4SI "V4HI")])
(define_mode_attr V_sz_elem1 [(V16QI "b") (V8HI "h") (V4SI "w") (V8HF "h")
(V4SF "w")])
(define_mode_attr V_extr_elem [(V16QI "u8") (V8HI "u16") (V4SI "32")
(V8HF "u16") (V4SF "32")])
(define_mode_attr earlyclobber_32 [(V16QI "=w") (V8HI "=w") (V4SI "=&w")
(V8HF "=w") (V4SF "=&w")])
(define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U])
(define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S])
(define_int_iterator VREV64Q [VREV64Q_S VREV64Q_U])
(define_int_iterator VCVTQ_FROM_F [VCVTQ_FROM_F_S VCVTQ_FROM_F_U])
(define_int_iterator VREV16Q [VREV16Q_U VREV16Q_S])
(define_int_iterator VCVTAQ [VCVTAQ_U VCVTAQ_S])
(define_int_iterator VMVNQ [VMVNQ_U VMVNQ_S])
(define_int_iterator VDUPQ_N [VDUPQ_N_U VDUPQ_N_S])
(define_int_iterator VCLZQ [VCLZQ_U VCLZQ_S])
(define_int_iterator VADDVQ [VADDVQ_U VADDVQ_S])
(define_int_iterator VREV32Q [VREV32Q_U VREV32Q_S])
(define_int_iterator VMOVLBQ [VMOVLBQ_S VMOVLBQ_U])
(define_int_iterator VMOVLTQ [VMOVLTQ_U VMOVLTQ_S])
(define_int_iterator VCVTPQ [VCVTPQ_S VCVTPQ_U])
(define_int_iterator VCVTNQ [VCVTNQ_S VCVTNQ_U])
(define_int_iterator VCVTMQ [VCVTMQ_S VCVTMQ_U])
(define_int_iterator VADDLVQ [VADDLVQ_U VADDLVQ_S])
(define_int_iterator VCTPQ [VCTP8Q VCTP16Q VCTP32Q VCTP64Q])
(define_int_iterator VCTPQ_M [VCTP8Q_M VCTP16Q_M VCTP32Q_M VCTP64Q_M])
(define_int_iterator VCVTQ_N_TO_F [VCVTQ_N_TO_F_S VCVTQ_N_TO_F_U])
(define_int_iterator VCREATEQ [VCREATEQ_U VCREATEQ_S])
(define_int_iterator VSHRQ_N [VSHRQ_N_S VSHRQ_N_U])
(define_int_iterator VCVTQ_N_FROM_F [VCVTQ_N_FROM_F_S VCVTQ_N_FROM_F_U])
(define_int_iterator VADDLVQ_P [VADDLVQ_P_S VADDLVQ_P_U])
(define_int_iterator VCMPNEQ [VCMPNEQ_U VCMPNEQ_S])
(define_int_iterator VSHLQ [VSHLQ_S VSHLQ_U])
(define_int_iterator VABDQ [VABDQ_S VABDQ_U])
(define_int_iterator VADDQ_N [VADDQ_N_S VADDQ_N_U])
(define_int_iterator VADDVAQ [VADDVAQ_S VADDVAQ_U])
(define_int_iterator VADDVQ_P [VADDVQ_P_U VADDVQ_P_S])
(define_int_iterator VANDQ [VANDQ_U VANDQ_S])
(define_int_iterator VBICQ [VBICQ_S VBICQ_U])
(define_int_iterator VBRSRQ_N [VBRSRQ_N_U VBRSRQ_N_S])
(define_int_iterator VCADDQ_ROT270 [VCADDQ_ROT270_S VCADDQ_ROT270_U])
(define_int_iterator VCADDQ_ROT90 [VCADDQ_ROT90_U VCADDQ_ROT90_S])
(define_int_iterator VCMPEQQ [VCMPEQQ_U VCMPEQQ_S])
(define_int_iterator VCMPEQQ_N [VCMPEQQ_N_S VCMPEQQ_N_U])
(define_int_iterator VCMPNEQ_N [VCMPNEQ_N_U VCMPNEQ_N_S])
(define_int_iterator VEORQ [VEORQ_U VEORQ_S])
(define_int_iterator VHADDQ [VHADDQ_S VHADDQ_U])
(define_int_iterator VHADDQ_N [VHADDQ_N_U VHADDQ_N_S])
(define_int_iterator VHSUBQ [VHSUBQ_S VHSUBQ_U])
(define_int_iterator VHSUBQ_N [VHSUBQ_N_U VHSUBQ_N_S])
(define_int_iterator VMAXQ [VMAXQ_U VMAXQ_S])
(define_int_iterator VMAXVQ [VMAXVQ_U VMAXVQ_S])
(define_int_iterator VMINQ [VMINQ_S VMINQ_U])
(define_int_iterator VMINVQ [VMINVQ_U VMINVQ_S])
(define_int_iterator VMLADAVQ [VMLADAVQ_U VMLADAVQ_S])
(define_int_iterator VMULHQ [VMULHQ_S VMULHQ_U])
(define_int_iterator VMULLBQ_INT [VMULLBQ_INT_U VMULLBQ_INT_S])
(define_int_iterator VMULLTQ_INT [VMULLTQ_INT_U VMULLTQ_INT_S])
(define_int_iterator VMULQ [VMULQ_U VMULQ_S])
(define_int_iterator VMULQ_N [VMULQ_N_U VMULQ_N_S])
(define_int_iterator VORNQ [VORNQ_U VORNQ_S])
(define_int_iterator VORRQ [VORRQ_S VORRQ_U])
(define_int_iterator VQADDQ [VQADDQ_U VQADDQ_S])
(define_int_iterator VQADDQ_N [VQADDQ_N_S VQADDQ_N_U])
(define_int_iterator VQRSHLQ [VQRSHLQ_S VQRSHLQ_U])
(define_int_iterator VQRSHLQ_N [VQRSHLQ_N_S VQRSHLQ_N_U])
(define_int_iterator VQSHLQ [VQSHLQ_S VQSHLQ_U])
(define_int_iterator VQSHLQ_N [VQSHLQ_N_S VQSHLQ_N_U])
(define_int_iterator VQSHLQ_R [VQSHLQ_R_U VQSHLQ_R_S])
(define_int_iterator VQSUBQ [VQSUBQ_U VQSUBQ_S])
(define_int_iterator VQSUBQ_N [VQSUBQ_N_S VQSUBQ_N_U])
(define_int_iterator VRHADDQ [VRHADDQ_S VRHADDQ_U])
(define_int_iterator VRMULHQ [VRMULHQ_S VRMULHQ_U])
(define_int_iterator VRSHLQ [VRSHLQ_S VRSHLQ_U])
(define_int_iterator VRSHLQ_N [VRSHLQ_N_U VRSHLQ_N_S])
(define_int_iterator VRSHRQ_N [VRSHRQ_N_S VRSHRQ_N_U])
(define_int_iterator VSHLQ_N [VSHLQ_N_U VSHLQ_N_S])
(define_int_iterator VSHLQ_R [VSHLQ_R_S VSHLQ_R_U])
(define_int_iterator VSUBQ [VSUBQ_S VSUBQ_U])
(define_int_iterator VSUBQ_N [VSUBQ_N_S VSUBQ_N_U])
(define_int_iterator VADDLVAQ [VADDLVAQ_S VADDLVAQ_U])
(define_int_iterator VBICQ_N [VBICQ_N_S VBICQ_N_U])
(define_int_iterator VMLALDAVQ [VMLALDAVQ_U VMLALDAVQ_S])
(define_int_iterator VMLALDAVXQ [VMLALDAVXQ_U VMLALDAVXQ_S])
(define_int_iterator VMOVNBQ [VMOVNBQ_U VMOVNBQ_S])
(define_int_iterator VMOVNTQ [VMOVNTQ_S VMOVNTQ_U])
(define_int_iterator VORRQ_N [VORRQ_N_U VORRQ_N_S])
(define_int_iterator VQMOVNBQ [VQMOVNBQ_U VQMOVNBQ_S])
(define_int_iterator VQMOVNTQ [VQMOVNTQ_U VQMOVNTQ_S])
(define_int_iterator VSHLLBQ_N [VSHLLBQ_N_S VSHLLBQ_N_U])
(define_int_iterator VSHLLTQ_N [VSHLLTQ_N_U VSHLLTQ_N_S])
(define_int_iterator VRMLALDAVHQ [VRMLALDAVHQ_U VRMLALDAVHQ_S])
(define_int_iterator VBICQ_M_N [VBICQ_M_N_S VBICQ_M_N_U])
(define_int_iterator VCVTAQ_M [VCVTAQ_M_S VCVTAQ_M_U])
(define_int_iterator VCVTQ_M_TO_F [VCVTQ_M_TO_F_S VCVTQ_M_TO_F_U])
(define_int_iterator VQRSHRNBQ_N [VQRSHRNBQ_N_U VQRSHRNBQ_N_S])
(define_int_iterator VABAVQ [VABAVQ_S VABAVQ_U])
(define_int_iterator VSHLCQ [VSHLCQ_S VSHLCQ_U])
(define_int_iterator VRMLALDAVHAQ [VRMLALDAVHAQ_S VRMLALDAVHAQ_U])
(define_int_iterator VADDVAQ_P [VADDVAQ_P_S VADDVAQ_P_U])
(define_int_iterator VCLZQ_M [VCLZQ_M_S VCLZQ_M_U])
(define_int_iterator VCMPEQQ_M_N [VCMPEQQ_M_N_S VCMPEQQ_M_N_U])
(define_int_iterator VCMPEQQ_M [VCMPEQQ_M_S VCMPEQQ_M_U])
(define_int_iterator VCMPNEQ_M_N [VCMPNEQ_M_N_S VCMPNEQ_M_N_U])
(define_int_iterator VCMPNEQ_M [VCMPNEQ_M_S VCMPNEQ_M_U])
(define_int_iterator VDUPQ_M_N [VDUPQ_M_N_S VDUPQ_M_N_U])
(define_int_iterator VMAXVQ_P [VMAXVQ_P_S VMAXVQ_P_U])
(define_int_iterator VMINVQ_P [VMINVQ_P_S VMINVQ_P_U])
(define_int_iterator VMLADAVAQ [VMLADAVAQ_S VMLADAVAQ_U])
(define_int_iterator VMLADAVQ_P [VMLADAVQ_P_S VMLADAVQ_P_U])
(define_int_iterator VMLAQ_N [VMLAQ_N_S VMLAQ_N_U])
(define_int_iterator VMLASQ_N [VMLASQ_N_S VMLASQ_N_U])
(define_int_iterator VMVNQ_M [VMVNQ_M_S VMVNQ_M_U])
(define_int_iterator VPSELQ [VPSELQ_S VPSELQ_U])
(define_int_iterator VQDMLAHQ_N [VQDMLAHQ_N_S VQDMLAHQ_N_U])
(define_int_iterator VQRDMLAHQ_N [VQRDMLAHQ_N_S VQRDMLAHQ_N_U])
(define_int_iterator VQRDMLASHQ_N [VQRDMLASHQ_N_S VQRDMLASHQ_N_U])
(define_int_iterator VQRSHLQ_M_N [VQRSHLQ_M_N_S VQRSHLQ_M_N_U])
(define_int_iterator VQSHLQ_M_R [VQSHLQ_M_R_S VQSHLQ_M_R_U])
(define_int_iterator VREV64Q_M [VREV64Q_M_S VREV64Q_M_U])
(define_int_iterator VRSHLQ_M_N [VRSHLQ_M_N_S VRSHLQ_M_N_U])
(define_int_iterator VSHLQ_M_R [VSHLQ_M_R_S VSHLQ_M_R_U])
(define_int_iterator VSLIQ_N [VSLIQ_N_S VSLIQ_N_U])
(define_int_iterator VSRIQ_N [VSRIQ_N_S VSRIQ_N_U])
(define_int_iterator VMLALDAVQ_P [VMLALDAVQ_P_U VMLALDAVQ_P_S])
(define_int_iterator VQMOVNBQ_M [VQMOVNBQ_M_S VQMOVNBQ_M_U])
(define_int_iterator VMOVLTQ_M [VMOVLTQ_M_U VMOVLTQ_M_S])
(define_int_iterator VMOVNBQ_M [VMOVNBQ_M_U VMOVNBQ_M_S])
(define_int_iterator VRSHRNTQ_N [VRSHRNTQ_N_U VRSHRNTQ_N_S])
(define_int_iterator VORRQ_M_N [VORRQ_M_N_S VORRQ_M_N_U])
(define_int_iterator VREV32Q_M [VREV32Q_M_S VREV32Q_M_U])
(define_int_iterator VREV16Q_M [VREV16Q_M_S VREV16Q_M_U])
(define_int_iterator VQRSHRNTQ_N [VQRSHRNTQ_N_U VQRSHRNTQ_N_S])
(define_int_iterator VMOVNTQ_M [VMOVNTQ_M_U VMOVNTQ_M_S])
(define_int_iterator VMOVLBQ_M [VMOVLBQ_M_U VMOVLBQ_M_S])
(define_int_iterator VMLALDAVAQ [VMLALDAVAQ_S VMLALDAVAQ_U])
(define_int_iterator VQSHRNBQ_N [VQSHRNBQ_N_U VQSHRNBQ_N_S])
(define_int_iterator VSHRNBQ_N [VSHRNBQ_N_U VSHRNBQ_N_S])
(define_int_iterator VRSHRNBQ_N [VRSHRNBQ_N_S VRSHRNBQ_N_U])
(define_int_iterator VMLALDAVXQ_P [VMLALDAVXQ_P_U VMLALDAVXQ_P_S])
(define_int_iterator VQMOVNTQ_M [VQMOVNTQ_M_U VQMOVNTQ_M_S])
(define_int_iterator VMVNQ_M_N [VMVNQ_M_N_U VMVNQ_M_N_S])
(define_int_iterator VQSHRNTQ_N [VQSHRNTQ_N_U VQSHRNTQ_N_S])
(define_int_iterator VMLALDAVAXQ [VMLALDAVAXQ_S VMLALDAVAXQ_U])
(define_int_iterator VSHRNTQ_N [VSHRNTQ_N_S VSHRNTQ_N_U])
(define_int_iterator VCVTMQ_M [VCVTMQ_M_S VCVTMQ_M_U])
(define_int_iterator VCVTNQ_M [VCVTNQ_M_S VCVTNQ_M_U])
(define_int_iterator VCVTPQ_M [VCVTPQ_M_S VCVTPQ_M_U])
(define_int_iterator VCVTQ_M_N_FROM_F [VCVTQ_M_N_FROM_F_S VCVTQ_M_N_FROM_F_U])
(define_int_iterator VCVTQ_M_FROM_F [VCVTQ_M_FROM_F_U VCVTQ_M_FROM_F_S])
(define_int_iterator VRMLALDAVHQ_P [VRMLALDAVHQ_P_S VRMLALDAVHQ_P_U])
(define_int_iterator VADDLVAQ_P [VADDLVAQ_P_U VADDLVAQ_P_S])
(define_int_iterator VABAVQ_P [VABAVQ_P_S VABAVQ_P_U])
(define_int_iterator VSHLQ_M [VSHLQ_M_S VSHLQ_M_U])
(define_int_iterator VSRIQ_M_N [VSRIQ_M_N_S VSRIQ_M_N_U])
(define_int_iterator VSUBQ_M [VSUBQ_M_U VSUBQ_M_S])
(define_int_iterator VCVTQ_M_N_TO_F [VCVTQ_M_N_TO_F_U VCVTQ_M_N_TO_F_S])
(define_int_iterator VHSUBQ_M [VHSUBQ_M_S VHSUBQ_M_U])
(define_int_iterator VSLIQ_M_N [VSLIQ_M_N_U VSLIQ_M_N_S])
(define_int_iterator VRSHLQ_M [VRSHLQ_M_S VRSHLQ_M_U])
(define_int_iterator VMINQ_M [VMINQ_M_S VMINQ_M_U])
(define_int_iterator VMULLBQ_INT_M [VMULLBQ_INT_M_U VMULLBQ_INT_M_S])
(define_int_iterator VMULHQ_M [VMULHQ_M_S VMULHQ_M_U])
(define_int_iterator VMULQ_M [VMULQ_M_S VMULQ_M_U])
(define_int_iterator VHSUBQ_M_N [VHSUBQ_M_N_S VHSUBQ_M_N_U])
(define_int_iterator VHADDQ_M_N [VHADDQ_M_N_S VHADDQ_M_N_U])
(define_int_iterator VORRQ_M [VORRQ_M_S VORRQ_M_U])
(define_int_iterator VRMULHQ_M [VRMULHQ_M_U VRMULHQ_M_S])
(define_int_iterator VQADDQ_M [VQADDQ_M_U VQADDQ_M_S])
(define_int_iterator VRSHRQ_M_N [VRSHRQ_M_N_S VRSHRQ_M_N_U])
(define_int_iterator VQSUBQ_M_N [VQSUBQ_M_N_U VQSUBQ_M_N_S])
(define_int_iterator VADDQ_M [VADDQ_M_U VADDQ_M_S])
(define_int_iterator VORNQ_M [VORNQ_M_U VORNQ_M_S])
(define_int_iterator VRHADDQ_M [VRHADDQ_M_U VRHADDQ_M_S])
(define_int_iterator VQSHLQ_M [VQSHLQ_M_U VQSHLQ_M_S])
(define_int_iterator VANDQ_M [VANDQ_M_U VANDQ_M_S])
(define_int_iterator VBICQ_M [VBICQ_M_U VBICQ_M_S])
(define_int_iterator VSHLQ_M_N [VSHLQ_M_N_S VSHLQ_M_N_U])
(define_int_iterator VCADDQ_ROT270_M [VCADDQ_ROT270_M_U VCADDQ_ROT270_M_S])
(define_int_iterator VQRSHLQ_M [VQRSHLQ_M_U VQRSHLQ_M_S])
(define_int_iterator VQADDQ_M_N [VQADDQ_M_N_U VQADDQ_M_N_S])
(define_int_iterator VADDQ_M_N [VADDQ_M_N_S VADDQ_M_N_U])
(define_int_iterator VMAXQ_M [VMAXQ_M_S VMAXQ_M_U])
(define_int_iterator VQSUBQ_M [VQSUBQ_M_U VQSUBQ_M_S])
(define_int_iterator VMLASQ_M_N [VMLASQ_M_N_U VMLASQ_M_N_S])
(define_int_iterator VMLADAVAQ_P [VMLADAVAQ_P_U VMLADAVAQ_P_S])
(define_int_iterator VBRSRQ_M_N [VBRSRQ_M_N_U VBRSRQ_M_N_S])
(define_int_iterator VMULQ_M_N [VMULQ_M_N_U VMULQ_M_N_S])
(define_int_iterator VCADDQ_ROT90_M [VCADDQ_ROT90_M_U VCADDQ_ROT90_M_S])
(define_int_iterator VMULLTQ_INT_M [VMULLTQ_INT_M_S VMULLTQ_INT_M_U])
(define_int_iterator VEORQ_M [VEORQ_M_S VEORQ_M_U])
(define_int_iterator VSHRQ_M_N [VSHRQ_M_N_S VSHRQ_M_N_U])
(define_int_iterator VSUBQ_M_N [VSUBQ_M_N_S VSUBQ_M_N_U])
(define_int_iterator VHADDQ_M [VHADDQ_M_S VHADDQ_M_U])
(define_int_iterator VABDQ_M [VABDQ_M_S VABDQ_M_U])
(define_int_iterator VMLAQ_M_N [VMLAQ_M_N_S VMLAQ_M_N_U])
(define_int_iterator VQSHLQ_M_N [VQSHLQ_M_N_S VQSHLQ_M_N_U])
(define_int_iterator VMLALDAVAQ_P [VMLALDAVAQ_P_U VMLALDAVAQ_P_S])
(define_int_iterator VMLALDAVAXQ_P [VMLALDAVAXQ_P_U VMLALDAVAXQ_P_S])
(define_int_iterator VQRSHRNBQ_M_N [VQRSHRNBQ_M_N_U VQRSHRNBQ_M_N_S])
(define_int_iterator VQRSHRNTQ_M_N [VQRSHRNTQ_M_N_S VQRSHRNTQ_M_N_U])
(define_int_iterator VQSHRNBQ_M_N [VQSHRNBQ_M_N_U VQSHRNBQ_M_N_S])
(define_int_iterator VQSHRNTQ_M_N [VQSHRNTQ_M_N_S VQSHRNTQ_M_N_U])
(define_int_iterator VRSHRNBQ_M_N [VRSHRNBQ_M_N_U VRSHRNBQ_M_N_S])
(define_int_iterator VRSHRNTQ_M_N [VRSHRNTQ_M_N_U VRSHRNTQ_M_N_S])
(define_int_iterator VSHLLBQ_M_N [VSHLLBQ_M_N_U VSHLLBQ_M_N_S])
(define_int_iterator VSHLLTQ_M_N [VSHLLTQ_M_N_U VSHLLTQ_M_N_S])
(define_int_iterator VSHRNBQ_M_N [VSHRNBQ_M_N_S VSHRNBQ_M_N_U])
(define_int_iterator VSHRNTQ_M_N [VSHRNTQ_M_N_S VSHRNTQ_M_N_U])
(define_int_iterator VSTRWSBQ [VSTRWQSB_S VSTRWQSB_U])
(define_int_iterator VSTRBSOQ [VSTRBQSO_S VSTRBQSO_U])
(define_int_iterator VSTRBQ [VSTRBQ_S VSTRBQ_U])
(define_int_iterator VLDRBGOQ [VLDRBQGO_S VLDRBQGO_U])
(define_int_iterator VLDRBQ [VLDRBQ_S VLDRBQ_U])
(define_int_iterator VLDRWGBQ [VLDRWQGB_S VLDRWQGB_U])
(define_int_iterator VLD1Q [VLD1Q_S VLD1Q_U])
(define_int_iterator VLDRHGOQ [VLDRHQGO_S VLDRHQGO_U])
(define_int_iterator VLDRHGSOQ [VLDRHQGSO_S VLDRHQGSO_U])
(define_int_iterator VLDRHQ [VLDRHQ_S VLDRHQ_U])
(define_int_iterator VLDRWQ [VLDRWQ_S VLDRWQ_U])
(define_int_iterator VLDRDGBQ [VLDRDQGB_S VLDRDQGB_U])
(define_int_iterator VLDRDGOQ [VLDRDQGO_S VLDRDQGO_U])
(define_int_iterator VLDRDGSOQ [VLDRDQGSO_S VLDRDQGSO_U])
(define_int_iterator VLDRWGOQ [VLDRWQGO_S VLDRWQGO_U])
(define_int_iterator VLDRWGSOQ [VLDRWQGSO_S VLDRWQGSO_U])
(define_int_iterator VST1Q [VST1Q_S VST1Q_U])
(define_int_iterator VSTRHSOQ [VSTRHQSO_S VSTRHQSO_U])
(define_int_iterator VSTRHSSOQ [VSTRHQSSO_S VSTRHQSSO_U])
(define_int_iterator VSTRHQ [VSTRHQ_S VSTRHQ_U])
(define_int_iterator VSTRWQ [VSTRWQ_S VSTRWQ_U])
(define_int_iterator VSTRDSBQ [VSTRDQSB_S VSTRDQSB_U])
(define_int_iterator VSTRDSOQ [VSTRDQSO_S VSTRDQSO_U])
(define_int_iterator VSTRDSSOQ [VSTRDQSSO_S VSTRDQSSO_U])
(define_int_iterator VSTRWSOQ [VSTRWQSO_S VSTRWQSO_U])
(define_int_iterator VSTRWSSOQ [VSTRWQSSO_S VSTRWQSSO_U])
(define_int_iterator VSTRWSBWBQ [VSTRWQSBWB_S VSTRWQSBWB_U])
(define_int_iterator VLDRWGBWBQ [VLDRWQGBWB_S VLDRWQGBWB_U])
(define_int_iterator VSTRDSBWBQ [VSTRDQSBWB_S VSTRDQSBWB_U])
(define_int_iterator VLDRDGBWBQ [VLDRDQGBWB_S VLDRDQGBWB_U])
(define_int_iterator VADCIQ [VADCIQ_U VADCIQ_S])
(define_int_iterator VADCIQ_M [VADCIQ_M_U VADCIQ_M_S])
(define_int_iterator VSBCQ [VSBCQ_U VSBCQ_S])
(define_int_iterator VSBCQ_M [VSBCQ_M_U VSBCQ_M_S])
(define_int_iterator VSBCIQ [VSBCIQ_U VSBCIQ_S])
(define_int_iterator VSBCIQ_M [VSBCIQ_M_U VSBCIQ_M_S])
(define_int_iterator VADCQ [VADCQ_U VADCQ_S])
(define_int_iterator VADCQ_M [VADCQ_M_U VADCQ_M_S])
(define_int_iterator UQRSHLLQ [UQRSHLL_64 UQRSHLL_48])
(define_int_iterator SQRSHRLQ [SQRSHRL_64 SQRSHRL_48])
(define_int_iterator VSHLCQ_M [VSHLCQ_M_S VSHLCQ_M_U])
(define_insn "*mve_mov"
[(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Ux,w")
(match_operand:MVE_types 1 "general_operand" "w,r,w,Dn,Uxi,r,Dm,w,Ul"))]
"TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT"
{
if (which_alternative == 3 || which_alternative == 6)
{
int width, is_valid;
static char templ[40];
is_valid = simd_immediate_valid_for_move (operands[1], mode,
&operands[1], &width);
gcc_assert (is_valid != 0);
if (width == 0)
return "vmov.f32\t%q0, %1 @ ";
else
sprintf (templ, "vmov.i%d\t%%q0, %%x1 @ ", width);
return templ;
}
if (which_alternative == 4 || which_alternative == 7)
{
rtx ops[2];
int regno = (which_alternative == 7)
? REGNO (operands[1]) : REGNO (operands[0]);
ops[0] = operands[0];
ops[1] = operands[1];
if (mode == V2DFmode || mode == V2DImode)
{
if (which_alternative == 7)
{
ops[1] = gen_rtx_REG (DImode, regno);
output_asm_insn ("vstr.64\t%P1, %E0",ops);
}
else
{
ops[0] = gen_rtx_REG (DImode, regno);
output_asm_insn ("vldr.64\t%P0, %E1",ops);
}
}
else if (mode == TImode)
{
if (which_alternative == 7)
output_asm_insn ("vstr.64\t%q1, %E0",ops);
else
output_asm_insn ("vldr.64\t%q0, %E1",ops);
}
else
{
if (which_alternative == 7)
{
ops[1] = gen_rtx_REG (TImode, regno);
output_asm_insn ("vstr.\t%q1, %E0",ops);
}
else
{
ops[0] = gen_rtx_REG (TImode, regno);
output_asm_insn ("vldr.\t%q0, %E1",ops);
}
}
return "";
}
switch (which_alternative)
{
case 0:
return "vmov\t%q0, %q1";
case 1:
return "vmov\t%e0, %Q1, %R1 @ \;vmov\t%f0, %J1, %K1";
case 2:
return "vmov\t%Q0, %R0, %e1 @ \;vmov\t%J0, %K0, %f1";
case 5:
return output_move_quad (operands);
case 8:
return output_move_neon (operands);
default:
gcc_unreachable ();
return "";
}
}
[(set_attr "type" "mve_move,mve_move,mve_move,mve_move,mve_load,multiple,mve_move,mve_store,mve_load")
(set_attr "length" "4,8,8,4,8,8,4,4,4")
(set_attr "thumb2_pool_range" "*,*,*,*,1018,*,*,*,*")
(set_attr "neg_pool_range" "*,*,*,*,996,*,*,*,*")])
(define_insn "*mve_mov"
[(set (match_operand:MVE_types 0 "s_register_operand" "=w,w")
(vec_duplicate:MVE_types
(match_operand:SI 1 "nonmemory_operand" "r,i")))]
"TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT"
{
if (which_alternative == 0)
return "vdup.\t%q0, %1";
return "vmov.\t%q0, %1";
}
[(set_attr "length" "4,4")
(set_attr "type" "mve_move,mve_move")])
;;
;; [vst4q])
;;
(define_insn "mve_vst4q"
[(set (match_operand:XI 0 "neon_struct_operand" "=Um")
(unspec:XI [(match_operand:XI 1 "s_register_operand" "w")
(unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
VST4Q))
]
"TARGET_HAVE_MVE"
{
rtx ops[6];
int regno = REGNO (operands[1]);
ops[0] = gen_rtx_REG (TImode, regno);
ops[1] = gen_rtx_REG (TImode, regno+4);
ops[2] = gen_rtx_REG (TImode, regno+8);
ops[3] = gen_rtx_REG (TImode, regno+12);
rtx reg = operands[0];
while (reg && !REG_P (reg))
reg = XEXP (reg, 0);
gcc_assert (REG_P (reg));
ops[4] = reg;
ops[5] = operands[0];
/* Here in first three instructions data is stored to ops[4]'s location but
in the fourth instruction data is stored to operands[0], this is to
support the writeback. */
output_asm_insn ("vst40.\t{%q0, %q1, %q2, %q3}, [%4]\n\t"
"vst41.\t{%q0, %q1, %q2, %q3}, [%4]\n\t"
"vst42.\t{%q0, %q1, %q2, %q3}, [%4]\n\t"
"vst43.\t{%q0, %q1, %q2, %q3}, %5", ops);
return "";
}
[(set_attr "length" "16")])
;;
;; [vrndq_m_f])
;;
(define_insn "mve_vrndq_m_f"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
(match_operand:MVE_0 2 "s_register_operand" "w")
(match_operand:HI 3 "vpr_register_operand" "Up")]
VRNDQ_M_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vpst\;vrintzt.f%# %q0, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
;;
;; [vrndxq_f])
;;
(define_insn "mve_vrndxq_f"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
VRNDXQ_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vrintx.f%# %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vrndq_f])
;;
(define_insn "mve_vrndq_f"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
VRNDQ_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vrintz.f%# %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vrndpq_f])
;;
(define_insn "mve_vrndpq_f"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
VRNDPQ_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vrintp.f%# %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vrndnq_f])
;;
(define_insn "mve_vrndnq_f"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
VRNDNQ_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vrintn.f%# %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vrndmq_f])
;;
(define_insn "mve_vrndmq_f"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
VRNDMQ_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vrintm.f%# %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vrndaq_f])
;;
(define_insn "mve_vrndaq_f"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
VRNDAQ_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vrinta.f%# %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vrev64q_f])
;;
(define_insn "mve_vrev64q_f"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=&w")
(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
VREV64Q_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vrev64.%# %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vnegq_f])
;;
(define_insn "mve_vnegq_f"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
VNEGQ_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vneg.f%# %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vdupq_n_f])
;;
(define_insn "mve_vdupq_n_f"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
(unspec:MVE_0 [(match_operand: 1 "s_register_operand" "r")]
VDUPQ_N_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vdup.%# %q0, %1"
[(set_attr "type" "mve_move")
])
;;
;; [vabsq_f])
;;
(define_insn "mve_vabsq_f"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
VABSQ_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vabs.f%# %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vrev32q_f])
;;
(define_insn "mve_vrev32q_fv8hf"
[
(set (match_operand:V8HF 0 "s_register_operand" "=w")
(unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "w")]
VREV32Q_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vrev32.16 %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vcvttq_f32_f16])
;;
(define_insn "mve_vcvttq_f32_f16v4sf"
[
(set (match_operand:V4SF 0 "s_register_operand" "=w")
(unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")]
VCVTTQ_F32_F16))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vcvtt.f32.f16 %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vcvtbq_f32_f16])
;;
(define_insn "mve_vcvtbq_f32_f16v4sf"
[
(set (match_operand:V4SF 0 "s_register_operand" "=w")
(unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")]
VCVTBQ_F32_F16))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vcvtb.f32.f16 %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vcvtq_to_f_s, vcvtq_to_f_u])
;;
(define_insn "mve_vcvtq_to_f_"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
(unspec:MVE_0 [(match_operand: 1 "s_register_operand" "w")]
VCVTQ_TO_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vcvt.f%#.%# %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vrev64q_u, vrev64q_s])
;;
(define_insn "mve_vrev64q_"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=&w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
VREV64Q))
]
"TARGET_HAVE_MVE"
"vrev64.%# %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vcvtq_from_f_s, vcvtq_from_f_u])
;;
(define_insn "mve_vcvtq_from_f_"
[
(set (match_operand:MVE_5 0 "s_register_operand" "=w")
(unspec:MVE_5 [(match_operand: 1 "s_register_operand" "w")]
VCVTQ_FROM_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vcvt.%#.f%# %q0, %q1"
[(set_attr "type" "mve_move")
])
;; [vqnegq_s])
;;
(define_insn "mve_vqnegq_s"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
VQNEGQ_S))
]
"TARGET_HAVE_MVE"
"vqneg.s%# %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vqabsq_s])
;;
(define_insn "mve_vqabsq_s"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
VQABSQ_S))
]
"TARGET_HAVE_MVE"
"vqabs.s%# %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vnegq_s])
;;
(define_insn "mve_vnegq_s"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
VNEGQ_S))
]
"TARGET_HAVE_MVE"
"vneg.s%# %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vmvnq_u, vmvnq_s])
;;
(define_insn "mve_vmvnq_"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
VMVNQ))
]
"TARGET_HAVE_MVE"
"vmvn %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vdupq_n_u, vdupq_n_s])
;;
(define_insn "mve_vdupq_n_"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand: 1 "s_register_operand" "r")]
VDUPQ_N))
]
"TARGET_HAVE_MVE"
"vdup.%# %q0, %1"
[(set_attr "type" "mve_move")
])
;;
;; [vclzq_u, vclzq_s])
;;
(define_insn "mve_vclzq_"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
VCLZQ))
]
"TARGET_HAVE_MVE"
"vclz.i%# %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vclsq_s])
;;
(define_insn "mve_vclsq_s"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
VCLSQ_S))
]
"TARGET_HAVE_MVE"
"vcls.s%# %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vaddvq_s, vaddvq_u])
;;
(define_insn "mve_vaddvq_"
[
(set (match_operand:SI 0 "s_register_operand" "=Te")
(unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")]
VADDVQ))
]
"TARGET_HAVE_MVE"
"vaddv.%#\t%0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vabsq_s])
;;
(define_insn "mve_vabsq_s"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
VABSQ_S))
]
"TARGET_HAVE_MVE"
"vabs.s%#\t%q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vrev32q_u, vrev32q_s])
;;
(define_insn "mve_vrev32q_"
[
(set (match_operand:MVE_3 0 "s_register_operand" "=w")
(unspec:MVE_3 [(match_operand:MVE_3 1 "s_register_operand" "w")]
VREV32Q))
]
"TARGET_HAVE_MVE"
"vrev32.%#\t%q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vmovltq_u, vmovltq_s])
;;
(define_insn "mve_vmovltq_"
[
(set (match_operand: 0 "s_register_operand" "=w")
(unspec: [(match_operand:MVE_3 1 "s_register_operand" "w")]
VMOVLTQ))
]
"TARGET_HAVE_MVE"
"vmovlt.%# %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vmovlbq_s, vmovlbq_u])
;;
(define_insn "mve_vmovlbq_"
[
(set (match_operand: 0 "s_register_operand" "=w")
(unspec: [(match_operand:MVE_3 1 "s_register_operand" "w")]
VMOVLBQ))
]
"TARGET_HAVE_MVE"
"vmovlb.%# %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vcvtpq_s, vcvtpq_u])
;;
(define_insn "mve_vcvtpq_"
[
(set (match_operand:MVE_5 0 "s_register_operand" "=w")
(unspec:MVE_5 [(match_operand: 1 "s_register_operand" "w")]
VCVTPQ))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vcvtp.%#.f%# %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vcvtnq_s, vcvtnq_u])
;;
(define_insn "mve_vcvtnq_"
[
(set (match_operand:MVE_5 0 "s_register_operand" "=w")
(unspec:MVE_5 [(match_operand: 1 "s_register_operand" "w")]
VCVTNQ))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vcvtn.%#.f%# %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vcvtmq_s, vcvtmq_u])
;;
(define_insn "mve_vcvtmq_"
[
(set (match_operand:MVE_5 0 "s_register_operand" "=w")
(unspec:MVE_5 [(match_operand: 1 "s_register_operand" "w")]
VCVTMQ))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vcvtm.%#.f%# %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vcvtaq_u, vcvtaq_s])
;;
(define_insn "mve_vcvtaq_"
[
(set (match_operand:MVE_5 0 "s_register_operand" "=w")
(unspec:MVE_5 [(match_operand: 1 "s_register_operand" "w")]
VCVTAQ))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vcvta.%#.f%# %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vmvnq_n_u, vmvnq_n_s])
;;
(define_insn "mve_vmvnq_n_"
[
(set (match_operand:MVE_5 0 "s_register_operand" "=w")
(unspec:MVE_5 [(match_operand:HI 1 "immediate_operand" "i")]
VMVNQ_N))
]
"TARGET_HAVE_MVE"
"vmvn.i%# %q0, %1"
[(set_attr "type" "mve_move")
])
;;
;; [vrev16q_u, vrev16q_s])
;;
(define_insn "mve_vrev16q_v16qi"
[
(set (match_operand:V16QI 0 "s_register_operand" "=w")
(unspec:V16QI [(match_operand:V16QI 1 "s_register_operand" "w")]
VREV16Q))
]
"TARGET_HAVE_MVE"
"vrev16.8 %q0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vaddlvq_s vaddlvq_u])
;;
(define_insn "mve_vaddlvq_v4si"
[
(set (match_operand:DI 0 "s_register_operand" "=r")
(unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")]
VADDLVQ))
]
"TARGET_HAVE_MVE"
"vaddlv.32 %Q0, %R0, %q1"
[(set_attr "type" "mve_move")
])
;;
;; [vctp8q vctp16q vctp32q vctp64q])
;;
(define_insn "mve_vctpqhi"
[
(set (match_operand:HI 0 "vpr_register_operand" "=Up")
(unspec:HI [(match_operand:SI 1 "s_register_operand" "r")]
VCTPQ))
]
"TARGET_HAVE_MVE"
"vctp. %1"
[(set_attr "type" "mve_move")
])
;;
;; [vpnot])
;;
(define_insn "mve_vpnothi"
[
(set (match_operand:HI 0 "vpr_register_operand" "=Up")
(unspec:HI [(match_operand:HI 1 "vpr_register_operand" "0")]
VPNOT))
]
"TARGET_HAVE_MVE"
"vpnot"
[(set_attr "type" "mve_move")
])
;;
;; [vsubq_n_f])
;;
(define_insn "mve_vsubq_n_f"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
(match_operand: 2 "s_register_operand" "r")]
VSUBQ_N_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vsub.f %q0, %q1, %2"
[(set_attr "type" "mve_move")
])
;;
;; [vbrsrq_n_f])
;;
(define_insn "mve_vbrsrq_n_f"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
(match_operand:SI 2 "s_register_operand" "r")]
VBRSRQ_N_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vbrsr. %q0, %q1, %2"
[(set_attr "type" "mve_move")
])
;;
;; [vcvtq_n_to_f_s, vcvtq_n_to_f_u])
;;
(define_insn "mve_vcvtq_n_to_f_"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
(unspec:MVE_0 [(match_operand: 1 "s_register_operand" "w")
(match_operand:SI 2 "" "")]
VCVTQ_N_TO_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vcvt.f.\t%q0, %q1, %2"
[(set_attr "type" "mve_move")
])
;; [vcreateq_f])
;;
(define_insn "mve_vcreateq_f"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
(unspec:MVE_0 [(match_operand:DI 1 "s_register_operand" "r")
(match_operand:DI 2 "s_register_operand" "r")]
VCREATEQ_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vmov %q0[2], %q0[0], %Q2, %Q1\;vmov %q0[3], %q0[1], %R2, %R1"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
;;
;; [vcreateq_u, vcreateq_s])
;;
(define_insn "mve_vcreateq_"
[
(set (match_operand:MVE_1 0 "s_register_operand" "=w")
(unspec:MVE_1 [(match_operand:DI 1 "s_register_operand" "r")
(match_operand:DI 2 "s_register_operand" "r")]
VCREATEQ))
]
"TARGET_HAVE_MVE"
"vmov %q0[2], %q0[0], %Q2, %Q1\;vmov %q0[3], %q0[1], %R2, %R1"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
;;
;; [vshrq_n_s, vshrq_n_u])
;;
(define_insn "mve_vshrq_n_"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:SI 2 "" "")]
VSHRQ_N))
]
"TARGET_HAVE_MVE"
"vshr.\t%q0, %q1, %2"
[(set_attr "type" "mve_move")
])
;;
;; [vcvtq_n_from_f_s, vcvtq_n_from_f_u])
;;
(define_insn "mve_vcvtq_n_from_f_"
[
(set (match_operand:MVE_5 0 "s_register_operand" "=w")
(unspec:MVE_5 [(match_operand: 1 "s_register_operand" "w")
(match_operand:SI 2 "" "")]
VCVTQ_N_FROM_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vcvt..f\t%q0, %q1, %2"
[(set_attr "type" "mve_move")
])
;;
;; [vaddlvq_p_s])
;;
(define_insn "mve_vaddlvq_p_v4si"
[
(set (match_operand:DI 0 "s_register_operand" "=r")
(unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
(match_operand:HI 2 "vpr_register_operand" "Up")]
VADDLVQ_P))
]
"TARGET_HAVE_MVE"
"vpst\;vaddlvt.32 %Q0, %R0, %q1"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
;;
;; [vcmpneq_u, vcmpneq_s])
;;
(define_insn "mve_vcmpneq_"
[
(set (match_operand:HI 0 "vpr_register_operand" "=Up")
(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:MVE_2 2 "s_register_operand" "w")]
VCMPNEQ))
]
"TARGET_HAVE_MVE"
"vcmp.i%# ne, %q1, %q2"
[(set_attr "type" "mve_move")
])
;;
;; [vshlq_s, vshlq_u])
;;
(define_insn "mve_vshlq_"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:MVE_2 2 "s_register_operand" "w")]
VSHLQ))
]
"TARGET_HAVE_MVE"
"vshl.%#\t%q0, %q1, %q2"
[(set_attr "type" "mve_move")
])
;;
;; [vabdq_s, vabdq_u])
;;
(define_insn "mve_vabdq_"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:MVE_2 2 "s_register_operand" "w")]
VABDQ))
]
"TARGET_HAVE_MVE"
"vabd.%# %q0, %q1, %q2"
[(set_attr "type" "mve_move")
])
;;
;; [vaddq_n_s, vaddq_n_u])
;;
(define_insn "mve_vaddq_n_"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand: 2 "s_register_operand" "r")]
VADDQ_N))
]
"TARGET_HAVE_MVE"
"vadd.i%# %q0, %q1, %2"
[(set_attr "type" "mve_move")
])
;;
;; [vaddvaq_s, vaddvaq_u])
;;
(define_insn "mve_vaddvaq_"
[
(set (match_operand:SI 0 "s_register_operand" "=Te")
(unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
(match_operand:MVE_2 2 "s_register_operand" "w")]
VADDVAQ))
]
"TARGET_HAVE_MVE"
"vaddva.%# %0, %q2"
[(set_attr "type" "mve_move")
])
;;
;; [vaddvq_p_u, vaddvq_p_s])
;;
(define_insn "mve_vaddvq_p_"
[
(set (match_operand:SI 0 "s_register_operand" "=Te")
(unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:HI 2 "vpr_register_operand" "Up")]
VADDVQ_P))
]
"TARGET_HAVE_MVE"
"vpst\;vaddvt.%# %0, %q1"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
;;
;; [vandq_u, vandq_s])
;;
(define_insn "mve_vandq_"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:MVE_2 2 "s_register_operand" "w")]
VANDQ))
]
"TARGET_HAVE_MVE"
"vand %q0, %q1, %q2"
[(set_attr "type" "mve_move")
])
;;
;; [vbicq_s, vbicq_u])
;;
(define_insn "mve_vbicq_"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:MVE_2 2 "s_register_operand" "w")]
VBICQ))
]
"TARGET_HAVE_MVE"
"vbic %q0, %q1, %q2"
[(set_attr "type" "mve_move")
])
;;
;; [vbrsrq_n_u, vbrsrq_n_s])
;;
(define_insn "mve_vbrsrq_n_"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:SI 2 "s_register_operand" "r")]
VBRSRQ_N))
]
"TARGET_HAVE_MVE"
"vbrsr.%# %q0, %q1, %2"
[(set_attr "type" "mve_move")
])
;;
;; [vcaddq_rot270_s, vcaddq_rot270_u])
;;
(define_insn "mve_vcaddq_rot270_"
[
(set (match_operand:MVE_2 0 "s_register_operand" "")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:MVE_2 2 "s_register_operand" "w")]
VCADDQ_ROT270))
]
"TARGET_HAVE_MVE"
"vcadd.i%# %q0, %q1, %q2, #270"
[(set_attr "type" "mve_move")
])
;;
;; [vcaddq_rot90_u, vcaddq_rot90_s])
;;
(define_insn "mve_vcaddq_rot90_"
[
(set (match_operand:MVE_2 0 "s_register_operand" "")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:MVE_2 2 "s_register_operand" "w")]
VCADDQ_ROT90))
]
"TARGET_HAVE_MVE"
"vcadd.i%# %q0, %q1, %q2, #90"
[(set_attr "type" "mve_move")
])
;;
;; [vcmpcsq_n_u])
;;
(define_insn "mve_vcmpcsq_n_u"
[
(set (match_operand:HI 0 "vpr_register_operand" "=Up")
(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand: 2 "s_register_operand" "r")]
VCMPCSQ_N_U))
]
"TARGET_HAVE_MVE"
"vcmp.u%# cs, %q1, %2"
[(set_attr "type" "mve_move")
])
;;
;; [vcmpcsq_u])
;;
(define_insn "mve_vcmpcsq_u"
[
(set (match_operand:HI 0 "vpr_register_operand" "=Up")
(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:MVE_2 2 "s_register_operand" "w")]
VCMPCSQ_U))
]
"TARGET_HAVE_MVE"
"vcmp.u%# cs, %q1, %q2"
[(set_attr "type" "mve_move")
])
;;
;; [vcmpeqq_n_s, vcmpeqq_n_u])
;;
(define_insn "mve_vcmpeqq_n_"
[
(set (match_operand:HI 0 "vpr_register_operand" "=Up")
(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand: 2 "s_register_operand" "r")]
VCMPEQQ_N))
]
"TARGET_HAVE_MVE"
"vcmp.i%# eq, %q1, %2"
[(set_attr "type" "mve_move")
])
;;
;; [vcmpeqq_u, vcmpeqq_s])
;;
(define_insn "mve_vcmpeqq_"
[
(set (match_operand:HI 0 "vpr_register_operand" "=Up")
(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:MVE_2 2 "s_register_operand" "w")]
VCMPEQQ))
]
"TARGET_HAVE_MVE"
"vcmp.i%# eq, %q1, %q2"
[(set_attr "type" "mve_move")
])
;;
;; [vcmpgeq_n_s])
;;
(define_insn "mve_vcmpgeq_n_s"
[
(set (match_operand:HI 0 "vpr_register_operand" "=Up")
(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand: 2 "s_register_operand" "r")]
VCMPGEQ_N_S))
]
"TARGET_HAVE_MVE"
"vcmp.s%# ge, %q1, %2"
[(set_attr "type" "mve_move")
])
;;
;; [vcmpgeq_s])
;;
(define_insn "mve_vcmpgeq_s"
[
(set (match_operand:HI 0 "vpr_register_operand" "=Up")
(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:MVE_2 2 "s_register_operand" "w")]
VCMPGEQ_S))
]
"TARGET_HAVE_MVE"
"vcmp.s%# ge, %q1, %q2"
[(set_attr "type" "mve_move")
])
;;
;; [vcmpgtq_n_s])
;;
(define_insn "mve_vcmpgtq_n_s"
[
(set (match_operand:HI 0 "vpr_register_operand" "=Up")
(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand: 2 "s_register_operand" "r")]
VCMPGTQ_N_S))
]
"TARGET_HAVE_MVE"
"vcmp.s%# gt, %q1, %2"
[(set_attr "type" "mve_move")
])
;;
;; [vcmpgtq_s])
;;
(define_insn "mve_vcmpgtq_s"
[
(set (match_operand:HI 0 "vpr_register_operand" "=Up")
(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:MVE_2 2 "s_register_operand" "w")]
VCMPGTQ_S))
]
"TARGET_HAVE_MVE"
"vcmp.s%# gt, %q1, %q2"
[(set_attr "type" "mve_move")
])
;;
;; [vcmphiq_n_u])
;;
(define_insn "mve_vcmphiq_n_u"
[
(set (match_operand:HI 0 "vpr_register_operand" "=Up")
(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand: 2 "s_register_operand" "r")]
VCMPHIQ_N_U))
]
"TARGET_HAVE_MVE"
"vcmp.u%# hi, %q1, %2"
[(set_attr "type" "mve_move")
])
;;
;; [vcmphiq_u])
;;
(define_insn "mve_vcmphiq_u"
[
(set (match_operand:HI 0 "vpr_register_operand" "=Up")
(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:MVE_2 2 "s_register_operand" "w")]
VCMPHIQ_U))
]
"TARGET_HAVE_MVE"
"vcmp.u%# hi, %q1, %q2"
[(set_attr "type" "mve_move")
])
;;
;; [vcmpleq_n_s])
;;
(define_insn "mve_vcmpleq_n_s"
[
(set (match_operand:HI 0 "vpr_register_operand" "=Up")
(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand: 2 "s_register_operand" "r")]
VCMPLEQ_N_S))
]
"TARGET_HAVE_MVE"
"vcmp.s%# le, %q1, %2"
[(set_attr "type" "mve_move")
])
;;
;; [vcmpleq_s])
;;
(define_insn "mve_vcmpleq_s"
[
(set (match_operand:HI 0 "vpr_register_operand" "=Up")
(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:MVE_2 2 "s_register_operand" "w")]
VCMPLEQ_S))
]
"TARGET_HAVE_MVE"
"vcmp.s%# le, %q1, %q2"
[(set_attr "type" "mve_move")
])
;;
;; [vcmpltq_n_s])
;;
(define_insn "mve_vcmpltq_n_s"
[
(set (match_operand:HI 0 "vpr_register_operand" "=Up")
(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand: 2 "s_register_operand" "r")]
VCMPLTQ_N_S))
]
"TARGET_HAVE_MVE"
"vcmp.s%# lt, %q1, %2"
[(set_attr "type" "mve_move")
])
;;
;; [vcmpltq_s])
;;
(define_insn "mve_vcmpltq_s"
[
(set (match_operand:HI 0 "vpr_register_operand" "=Up")
(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:MVE_2 2 "s_register_operand" "w")]
VCMPLTQ_S))
]
"TARGET_HAVE_MVE"
"vcmp.s%# lt, %q1, %q2"
[(set_attr "type" "mve_move")
])
;;
;; [vcmpneq_n_u, vcmpneq_n_s])
;;
(define_insn "mve_vcmpneq_n_"
[
(set (match_operand:HI 0 "vpr_register_operand" "=Up")
(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand: 2 "s_register_operand" "r")]
VCMPNEQ_N))
]
"TARGET_HAVE_MVE"
"vcmp.i%# ne, %q1, %2"
[(set_attr "type" "mve_move")
])
;;
;; [veorq_u, veorq_s])
;;
(define_insn "mve_veorq_"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:MVE_2 2 "s_register_operand" "w")]
VEORQ))
]
"TARGET_HAVE_MVE"
"veor %q0, %q1, %q2"
[(set_attr "type" "mve_move")
])
;;
;; [vhaddq_n_u, vhaddq_n_s])
;;
(define_insn "mve_vhaddq_n_"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand: 2 "s_register_operand" "r")]
VHADDQ_N))
]
"TARGET_HAVE_MVE"
"vhadd.%#\t%q0, %q1, %2"
[(set_attr "type" "mve_move")
])
;;
;; [vhaddq_s, vhaddq_u])
;;
(define_insn "mve_vhaddq_"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:MVE_2 2 "s_register_operand" "w")]
VHADDQ))
]
"TARGET_HAVE_MVE"
"vhadd.%#\t%q0, %q1, %q2"
[(set_attr "type" "mve_move")
])
;;
;; [vhcaddq_rot270_s])
;;
(define_insn "mve_vhcaddq_rot270_s"
[
(set (match_operand:MVE_2 0 "s_register_operand" "")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:MVE_2 2 "s_register_operand" "w")]
VHCADDQ_ROT270_S))
]
"TARGET_HAVE_MVE"
"vhcadd.s%#\t%q0, %q1, %q2, #270"
[(set_attr "type" "mve_move")
])
;;
;; [vhcaddq_rot90_s])
;;
(define_insn "mve_vhcaddq_rot90_s